Our client was founded with the ideals of providing true value to clients in product and design services across industries.
They have achieved this by building a world class engineering team with intensive knowledge in Chip Design, Embedded Software and Hardware. Thier ability to execute complex turnkey projects with a steadfast focus on quality is what differentiates them
Our client has a strong focus on R&D initiatives that are aligned with the market requirements and it helps us work in areas of high complexity in Chip Design and Embedded Systems.
Our client is well funded by a group of companies which have been in business for more than 50 years and are market leaders in their fields
Chip integration of high complexity SOCs.
Coordinating with various IP owners on receivables and DV, synthesis and Emulation for deliverables
Spyglass/CDC for the full chip and will evaluate the incoming bugs and take appropriate action
Formal Verification between RTL to Netlist and Netlist to Netlist
Manual and Conformal ECO
Running Lint (Spyglass) at SoC level.
Chip level integration and connectivity.
Debugging FV failures
Desired Skills And Experience-
2 – 7 years of experience
Sound knowledge in Micro Architecture design and RTL implementatio
Understanding of ARM SoCs with AXI/AHB buses, peripherals, CPUs and mobile SOCs is desirable
Experience in Synthesis and pre-layout timing analysis
Understanding of DFT flow is desirable
Experiencing using clear case a must
Experienced with VHDL/Verilog/coding and tools like VCS/Verdi/Spyglass/Mentor Zero-in
Proficiency in LEC and formal flows.
Experience in Perl, TCL and shell scripting
Excellent interpersonal & analytical skills with ability to work independently
“Mining the Knowledge Community”
Salary: ₹ Not Disclosed by Recruiter
[Apply here ]